In recent years, extensive studies have been performed on development of a nonvolatile semiconductor memory device with a BiCS (Bit Cost Scalable) structure for increasing the capacity and cutting the cost by adopting a three-dimensional structure. The nonvolatile semiconductor memory device with the BiCS structure is prepared by processing of a laminate structure having a conductive word line layer and inter-word line insulating film, so that it is possible to minimize the cost on a per bit basis while increasing the number of layers in the laminate structure.
However, when the laminate structure is etched, the perpendicularity of the etching degrades, so that the hole cross-sectional area may be different at different depths of the laminate structure. As a result, the size of the cross-sectional area of silicon pillars arranged in the laminate may vary, and the threshold voltage of the memory cells may vary corresponding to the height of the laminate. Consequently, when deletion is performed for a block of memory cells on the various layers at a constant voltage, an over-deletion state occurs in some of the memory cells, leading to degradation in the reliability of the nonvolatile semiconductor memory device.